The present invention relates generally to data communication interface devices for use in systems where data time-varying in predetermined cycles, such as digital audio data, are transmitted to and from a communication network in packets, and also relates to a data communication system and a data communication node include the data communication interface devices.
Data communication techniques using a communication network can be classified roughly into the synchronous type and the asynchronous type. According to the synchronous-type data communication technique, a dedicated synchronizing signal line etc. are provided between transmitting and receiving ends and data are transmitted in response to each synchronizing signal so that the receiving end is allowed to accurately reproduce original data on the basis of the transmitted data. Thus, the synchronous-type data communication technique is suitable for communication of digital audio data and the like for which accurate reproduction of respective time positions of the individual data is required at the receiving end. However, this synchronous-type data communication technique requires separate provision of the synchronizing signal line and other arrangements for synchronizing the transmitting and receiving ends. Further, because the line during communication is occupied by the communication alone, the synchronous-type data communication technique lacks versatility as a means of communication.
The asynchronous-type data communication technique, on the other hand, is suitable for transmission of text data and still picture data such as in personal-computer to personal-computer communication, because it does not require provision of a dedicated synchronizing signal line and the like. However, the asynchronous-type data communication technique can not be suitably used for communication of digital audio data, because information indicative of original time positions of the data would be lost in packet transmission employed in this type of communication.
To avoid the problems encountered by the synchronous-and asynchronous-type data communication technique, a pseudo-synchronous-type data communication technique is employed nowadays. According to this pseudo-synchronous-type data communication technique, each individual node includes a clock oscillator circuit and a clock counter for counting clock pulses generated by the clock oscillator circuit. The transmitting-end node produces a data packet with time data (time stamp), indicative of its time position, attached thereto and transmits the thus-produced data packet onto a communication network data. The receiving-end node compares the time data and a count value of its internal clock counter, modifies the count value with the time data when the compared values have been determined as not identical to or matching each other, and then sequentially reproduces the data on the basis of the thus-modified count value. Such a pseudo-synchronous-type data communication technique is also called an xe2x80x9cisochronousxe2x80x9d data communication technique, the IEEE1394 protocol is one of the known protocols defining the isochronous data communication technique.
Specifically, because the clock oscillator circuits of the individual networked nodes do not always oscillate at completely the same frequency and some discrepancies may exist between the clock pulse generation timing in these nodes, the pseudo-synchronous-type data communication technique, at each synchronization timing, i.e., upon reception of each time data, adjusts the clock pulse counts in conformity with the time data, to thereby eliminate the discrepancies.
Further, in the pseudo-synchronous-type data communication technique, a FIFO memory capable of storing data of one or more packets is normally provided on a chip constituting an interface device, so as to carry out data transmission/reception on a packet-by-packet basis. Access to the packet data in the FIFO memory is executed via a CPU or a peripheral I/O device. Thus, it is necessary that the FIFO memory have an optimum capacity or size depending on the application.
However, because a more-than-necessary size is allocated to the FIFO memory in order to give priority to the versatility of the chip, the conventional pseudo-synchronous-type data communication technique presents the problem that the FIFO memory would be used wastefully. Conversely, when it is desired to increase the number of connection channels to digital audio equipment, the FIFO memory size is too small to permit a substantial increase in the number of channels. Typical examples of the conventional data communication system using a communication network are disclosed in, for example, U.S. Pat. No. 5,616,879 and Japanese Patent Publication No. HEI-9-93250.
It is therefore an object of the present invention to provide a data communication interface device which is capable of freely varying a buffer storage size depending on an application and thereby permits data communication with increased efficiency.
It is a further object of the present invention to provide a data communication system and/or a data communication node which use the data communication interface device.
In order to accomplish the above-mentioned object, the present invention provides a data communication interface device for use in at least one of a transmitting node and a receiving node to execute data packet communication between a plurality of nodes via a communication network, which communication interface device comprises: at least one interface chip including a storage section that has a predetermined capacity for buffering a data packet to be transmitted or having been received via the communication network; and a control section that controls the at least one interface chip to thereby control transmission or reception of the data packet to or from the communication network. The total number of the interface chip to be connected to the control section is optionally selectable in such a manner that an overall buffer storage size in the data communication interface device can be adjusted freely by just increasing or decreasing the number of the interface chips. With this arrangement, users can construct an efficient, i.e., waste-free, data communication interface device by just increasing or decreasing the number of the interface chips depending on an application.
For example, where data having a relatively high speed and relatively great size, such as digital audio data, are to be transmitted/received for a plurality of channels, the desired data communication can be carried out by connecting, to the control section, a necessary number of the interface chips each including a storage section of a relatively great capacity. Thus, the overall buffer storage size in the data communication interface device can be apparently increased to permit communication of the great-size data. Further, where data having a relatively low speed and relatively small size, such as MIDI data, are to be transmitted/received for a plurality of channels, the desired data communication can be carried out by connecting, to the control section, a necessary number of the interface chips each including a storage section of a relatively small capacity. Moreover, where it is desired to transmit/receive both great-size data such as digital audio data and small-size data such as MIDI data, the desired communication can be carried out by connecting, to the control section, necessary numbers of the interface chips each including a storage section of a relatively great capacity and the interface chips each including a storage section of a relatively small capacity.
It will be appreciated that the number of the interface chips to be connected to the control section may be determined depending on the capacity of the respective storage sections of the chips. Further, different types of data can be transmitted/received by allocating, to each of the data types, a different interface chip (or chips) to be used for transmission/reception of that type of data. Moreover, a plurality of the interface chips, whose respective buffers have different sizes (i.e., whose respective storage sections have different capacity), may be connected to the control section, so as to provide combinations or groups of the interface chips that are optimal for transmission/reception of the data of the individual types.